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1 for more information www.linear.com/LT3063 typical a pplica t ion fea t ures descrip t ion 45v v in , micr opower , low noise, 200ma ldo with output dischar ge the lt ? 3063 is a micropower, low dropout ( ldo) linear regulator that operates over a 1.6 v to 45 v supply range . the device supplies 200 ma of output current with a typi - cal dropout voltage of 300 mv. a single external capacitor provides programmable low noise reference per formance and output soft - start functionality. the LT3063 s quiescent current is merely 45 a and provides fast transient response with a minimum 3.3 f output capacitor. in shutdown, quiescent current is less than 3 a and the reference soft start capacitor is reset. the LT3063 features an nmos pull-down that discharges the output if shdn or in is driven low. internal protection cir cuitr y includes reverse - batter y protec - tion, reverse - current protection, current limit with foldback and thermal shutdown . the LT3063 is available as an adjustable device with an output voltage range from the 600 mv reference up to 19 v. the LT3063 is offered in the thermally enhanced 8- lead 2mm 3mm dfn and msop packages. 1.8v low noise regulator a pplica t ions n input voltage range: 1.6v to 45v n output current: 200ma n output discharge n quiescent current: 45a n dropout voltage: 300mv n low noise: 30v rms (10hz to 100khz) n adjustable output (v ref = 600mv) n output tolerance: 2% over load, line, and temperature n single capacitor soft-starts reference and lowers output noise n shutdown current < 3a n reverse battery protection n current limit foldback and thermal limit protection n 8-lead 2mm 3mm dfn and msop packages n batter y powered systems n automotive power supplies n industrial power supplies n avionic power supplies n portable instruments n medical instruments l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 3063 ta01 in shdn out adj gnd byp l t3063 v in 2.3v v out 1.8v 200ma 1 f 10f 118k 1% 59k 1% 0.01 f output discharge vs v out c ref/byp = 0 1ms/div shdn : 0 to 1v 2v/div 12v 10v 8v 6v 5v 2v 1.2v 3.3v 0v 3063 ta01a v in = v out +1v c out = 10f i fb-divider = 10a lt 3063 3063f http://
2 for more information www.linear.com/LT3063 p in c on f igura t ion a bsolu t e maxi m u m r a t ings in pin voltage ......................................................... 50 v out pin voltage .............................................. +2 0 v , C1 v input to output differential voltage ( note 2) ........... 50 v adj pin voltage ...................................................... 50 v sh dn pin voltage ................................................... 50 v ref / byp pin voltage .................................... C 0. 3 v to 1 v output short - circuit duration .......................... in definite (note 1) top view gnd shdn in in ref/byp adj out out dcb package 8-lead (2mm 3mm) plastic dfn 9 gnd 3 4 2 1 6 5 7 8 t jmax = 150c, ja = 38c/w to 45c/w, jc = 3.5c/w exposed pa d ( pin 9) is gnd, must be soldered to pcb 1 2 3 4 ref/byp adj out out 8 7 6 5 gnd shdn in in top view ms8e p ackage 8-lead plastic msop 9 gnd t jmax = 150c, ja = 29c/w to 45c/w, jc = 5c/w to 10c/w exposed pad ( pin 9) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish t ape and reel pa r t marking* p ackage descrip tion tempera ture range LT3063edcb#pbf LT3063edcb#trpbf lgmz 8-lead (2mm 3mm) plastic dfn C40c to 125c LT3063idcb#pbf LT3063idcb#trpbf lgmz 8-lead (2mm 3mm) plastic dfn C40c to 125c LT3063hdcb#pbf LT3063hdcb#trpbf lgmz 8-lead (2mm 3mm) plastic dfn C40c to 150c LT3063mpdcb#pbf LT3063mpdcb#trpbf lgmz 8-lead (2mm 3mm) plastic dfn C55c to 150c LT3063ems8e#pbf LT3063ems8e#trpbf l tgnb 8-lead plastic msop C40c to 125c LT3063ims8e#pbf LT3063ims8e#trpbf l tgnb 8-lead plastic msop C40c to 125c LT3063hms8e#pbf LT3063hms8e#trpbf l tgnb 8-lead plastic msop C40c to 150c LT3063mpms8e#pbf LT3063mpms8e#trpbf l tgnb 8-lead plastic msop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o p e r a t in g jun c t i o n te m p e r a t u r e ( n ot es 3 , 5 , 1 2 ) lt 306 3 e, lt 3063 i ............................. C 40 c to 125 c lt 3063 mp ......................................... C 55 c to 150 c lt 306 3 h ............................................ C4 0 c to 150 c storage temperature range .................. C 6 5 c to 15 0 c lead temperature ( soldering , 10 sec ) ms 8e package only .......................................... 300 c lt 3063 3063f
3 for more information www.linear.com/LT3063 e lec t rical c harac t eris t ics p arameter conditions min ty p max units minimum input v oltage (note 4) i load = 200ma l 1.6 2.1 v adj pin v oltage (notes 4, 5) v in = 2.1v, i load = 1ma 2.1v < v in < 45v, 1ma < i load < 200ma (e-, i-grades) 2.1v < v in < 45v, 1ma < i load < 200ma (mp-, h-grades) l l 594 588 585 600 600 600 606 612 612 mv mv mv line regulation (note 4) v in = 2.1v to 45v, i load = 1ma (e-, i-grades) v in = 2.1v to 45v, i load = 1ma (mp-, h-grades) l l 0.5 4 6 mv mv load regulation (note 4) v in = 2.1v, i load = 1ma to 200ma (e-, i-grades) v in = 2.1v, i load = 1ma to 200ma (mp-, h-grades) l l 0.3 4 9 mv mv dropout v oltage v in = v out(nominal) (notes 6, 7) i load = 1ma i load = 1ma l 65 110 180 mv mv i load = 10ma i load = 10ma l 130 180 270 mv mv i load = 100ma i load = 100ma l 250 290 430 mv mv i load = 200ma i load = 200ma l 300 360 530 mv mv gnd pin current v in = v out(nominal) + 0.6v (notes 6, 8) i load = 0 i load = 1ma i load = 10ma i load = 100ma i load = 200ma l l l l l 45 70 225 2 5 90 120 500 4 10 a a a ma ma output v oltage noise c out = 10f, i load = 200ma, c ref/byp = 0.01f v out = 600mv, bw = 10hz to 100khz 30 v rms adj pin bias current (notes 4, 9) l 15 60 na shutdown threshold v out = off to on v out = on to off l l 0.3 0.8 0.7 1.5 v v shdn pin current (note 10) v shdn = 0v v shdn = 45v l l 1.2 <1 3 a a quiescent current in shutdown v in = 45v, v shdn = 0v 1.25 3 a ripple rejection (note 4) v in C v out = 1.5v (av g ), v ripple = 0.5v p-p , f ripple = 120hz, i load = 200ma 70 85 db current limit v in = 7v, v out = 0 v in = v out(nominal) + 1v (note 11), v out = C5% l 220 320 ma ma input reverse leakage current v in = -45v, v out = 0 l 1 ma output discharge t ime (note 6) v out discharged to 10% of nominal, c out = 10f l 0.75 2 ms reverse output current v out = 3.3v, v in = v shdn = 2.1v 2.5 15 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) lt 3063 3063f
4 for more information www.linear.com/LT3063 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: absolute maximum input to output differential voltage is not achievable with all combinations of rated in pin and out pin voltages. with the in pin at 50v, the out pin may not be pulled below 0v. the total measured voltage from in to out must not exceed 50v. note 3: the LT3063 is tested and specified under pulse load conditions such that t j ? t a . the LT3063e regulators are 100% tested at t a = 25c and per formance is guaranteed from 0c to 125c. per formance at C 40c to 125c is assured by design, characterization and correlation with statistical process controls. the LT3063i regulators are guaranteed over the full C 40c to 125c operating junction temperature range. the LT3063mp regulators are 100% tested over the C 55c to 150c operating junction temperature. the LT3063h regulators are 100% tested at the 150c operating junction temperature. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperature greater than 125c. note 4: the LT3063 is tested and specified for these conditions with the adj connected to the out pin. note 5: maximum junction temperature limits operating conditions. the regulated output voltage specification does not apply for all possible combinations of input voltage and output current. limit the output current range if operating at the maximum input voltage. limit the input-to-output voltage differential if operating at maximum output current. current limit foldback limits the maximum output current as a function of input-to- output voltage. see current limit vs v in C v out in the t ypical per formance characteristics section. note 6: to satisfy minimum input voltage requirements, the LT3063 is tested and specified for these conditions with an external resistor divider (bottom 60k, top 230k) for an output voltage of 2.9v. the external resistor divider adds 10a of dc load on the output. the external current is not factored into gnd pin current. note 7: dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage equals: (v in C v dropout ). note 8: gnd pin current is tested with v in = v out(nominal) + 0.6v and a current sour ce load. gnd pin current will increase in dropout. see gnd pin current cur ves in the t ypical per formance characteristics section. note 9: adj pin bias current flows out of the adj pin. note 10: shdn pin current flows into the shdn pin. note 11: to satisfy requirements for minimum input voltage, current limit is tested at v in = v out(nominal) + 1v or v in = 2.1v, whichever is greater. note 12: this ic includes thermal limit which protects the device during momentar y overload conditions. junction temperature exceeds 125c (LT3063e, LT3063i) or 150c (LT3063mp, LT3063h) when thermal limit is active. continuous operation above the specified maximum junction temperature may impair device reliability. lt 3063 3063f
5 for more information www.linear.com/LT3063 typical p er f or m ance c harac t eris t ics quiescent current adj pin v oltage quiescent current gnd pin current, v out = 0.6v gnd pin current vs i load shdn pin threshold t ypical dropout v oltage guaranteed dropout v oltage dropout v oltage output current (ma) 0 0 dropout vol t age (mv) 350 300 250 200 150 100 50 550 400 450 500 100 125 150 175 200 25 50 3063 g01 75 t j = 125c t j = 25c t j = 150c output current (ma) 0 0 dropout vol t age (mv) 350 300 250 200 150 100 50 550 500 450 400 25 125 150 175 200 50 75 3063 g02 100 t j = 25c t j = 150c = test points temperature (c) ?75 0 dropout vol t age (mv) 350 400 300 250 200 150 100 50 550 450 500 ?50 75 100 125 150 175 ?25 0 25 3063 g03 50 i l = 200ma i l = 50ma i l = 10ma i l = 100ma temperature (c) ?75 0 quiescent current (a) 60 50 40 30 20 10 80 70 ?50 75 100 125 150 175 ?25 0 25 3063 g04 50 v in = v shdn = 6v v out = 5v i l = 10a v in = 6v all other pins = 0v temperature (c) ?75 588 adj pin vol t age (mv) 608 606 604 594 596 598 600 602 592 590 612 610 ?50 75 100 125 150 175 ?25 0 25 3063 g05 50 i l = 1ma v in (v) 0 0 quiescent current (a) 100 90 80 30 40 50 60 70 20 10 120 110 5 25 30 35 40 45 10 15 3063 g06 20 t j = 25c v out = 5v i l = 10ma v shdn = 0v, r l = 0 r l = 3, i l = 200ma r l = 6, i l = 100ma r l = 12, i l = 50ma r l = 600, i l = 1ma v in (v) 0 0 gnd pin current (ma) 4.0 3.5 3.0 0.5 1.0 1.5 2.0 2.5 5.0 4.5 2 1 6 7 8 9 10 3 4 3063 g07 5 i load (ma) 0 0 gnd pin current (ma) 9 8 3 2 1 4 5 6 7 10 25 100 125 150 175 200 50 3063 g08 75 v in = v out(nominal) +1v temperature (c) ?75 0 shdn pin threshold (v) 1.4 1.3 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.9 1.0 1.1 1.2 1.5 ?25 ?50 75 100 125 150 175 0 25 3063 g09 50 off to on on to off t a = 25c, unless otherwise noted. lt 3063 3063f
6 for more information www.linear.com/LT3063 typical p er f or m ance c harac t eris t ics internal current limit internal current limit output discharge t ime output discharge t ime c out = 10f, v in = v out + 1v output discharge vs v out c ref/byp = 0 output discharge vs v out c ref/byp = 0 shdn pin input current shdn pin input current adj pin bias current t a = 25c, unless other wise noted. shdn pin voltage (v) 0 0 shdn pin input current (a) 2.0 2.5 1.5 1.0 0.5 3.0 5 30 35 40 45 10 15 20 3063 g10 25 temperature (c) ?75 0 shdn pin input current (a) 2.0 2.5 1.5 1.0 0.5 3.0 ?50 75 100 125 150 175 ?25 0 25 3063 g11 50 shdn = 45v temperature (c) ?75 ?50 adj pin bias current (na) 30 10 0 ?10 ?20 ?30 ?40 20 50 40 ?25 ?50 75 100 125 150 175 0 25 3063 g12 50 input/output voltage differential (v) 0 0 current limit (ma) 300 250 200 50 100 150 400 350 5 25 30 35 40 45 10 15 3063 g13 20 t j = ?55c t j = ?40c t j = 25c t j = 125c t j = 150c temperature (c) ?75 0 current limit (ma) 450 400 250 300 150 200 100 50 350 500 ?25 ?50 75 100 125 150 175 0 25 3063 g14 50 v in = 7v v out = 0v output voltage (v) 0 0 output discharge time (ms) 3.5 1.0 1.5 2.0 2.5 3.0 0.5 4.0 2 10 12 14 16 18 20 4 6 3063 g15 8 c out = 10f v in = v out + 1v output discharge foldback starts temperature (c) ?75 0 output discharge time (ms) 5 4 3 1 2 7 6 ?25 ?50 75 100 125 150 175 0 25 3063 g16 50 out = 1.2v out = 3.3v out = 5v out = 12v out = 20v 1ms/div 2v/div 12v 0v 3063 g17 v in = v out +1v c out = 10f i fb-divider = 10a 12v 10v 8v 6v 5v 2v 3.3v 1.2v shdn : 0 to 1v 1ms/div 5v/div 20v 20v 15v 12v 0v 3063 g18 v in = v out +1v c out = 10f i fb-divider = 10a shdn : 0 to 1v lt 3063 3063f
7 for more information www.linear.com/LT3063 input ripple rejection reverse current t a = 25c, unless other wise noted. typical p er f or m ance c harac t eris t ics minimum input voltage load regulation 5v t ransient response c ff = 0, i out = 20ma to 200ma reverse current input ripple rejection input ripple rejection temperature (c) ?75 0 output current (a) 130 140 120 60 70 80 90 100 110 40 50 10 20 30 150 ?50 75 100 125 150 175 ?25 0 25 3063 g20 50 v out = v adj = 3.3v v in = v shdn = 2.1v i adj i out frequency (hz) 10 0 ripple rejection (db) 50 40 10 20 30 90 60 70 80 10k 100k 1m 10m 100 3063 g21 1k i load = 200ma c ref/byp = c ff = 0 v in = v out +1.5v +50mv rms v out = 0.6v v out = 5v c out = 10f c out = 3.3f v out (v) 0 0 output current (a) 45 40 30 35 20 25 5 10 15 50 2 12 14 16 18 20 4 6 8 3063 g19 10 v in = v shdn = 2.1v v adj = v out 5 v t ransient response c ff = 10 nf, i out = 20 ma to 200 ma frequency (hz) 10 0 ripple rejection (db) 50 40 10 20 30 100 60 70 80 90 10k 100k 1m 10m 100 3063 g22 1k c ref/byp = c ff = 0 c ref/byp = 10nf, c ff = 0 c ref/byp = 10nf, c ff = 10nf v in = 6.5v +50mv rms ripple i load = 200ma c out = 10f v out = 5v temperature (c) ?75 0 ripple rejection (db) 60 70 80 90 40 50 10 20 30 100 ?50 75 100 125 150 175 ?25 0 25 3063 g23 50 c ref/byp = 10nf c ref/byp = 0 i load = 200ma v out = 0.6v v in = 2.6v +0.5v p-p ripple, f = 120hz temperature (c) ?75 0.0 minimum input vol t age (v) 1.4 1.6 1.8 2.0 1.0 1.2 0.2 0.4 0.6 0.8 2.2 ?50 75 100 125 150 175 ?25 0 25 3063 g24 50 i load = 200ma i load = 100ma temperature (c) ?75 ?10 ?9 load regula tion (mv) ?1 0 ?2 ?8 ?7 ?6 ?5 ?4 ?3 1 ?50 75 100 125 150 175 ?25 0 25 3063 g25 50 ?i l = 1ma to 200ma v out = 0.6v v in = 2.1v 100s/div 3063 g26 v in = 6v c out = 10f i fb-divider = 10a v out 100mv/div i out 100ma/div 20s/div 3063 g27 v in = 6v c out = 10f i fb-divider = 10a v out 50mv/div i out 100ma/div lt 3063 3063f
8 for more information www.linear.com/LT3063 typical p er f or m ance c harac t eris t ics output noise spectral density vs c ff , c ref/byp = 10nf output noise spectral density c ref/byp = 0, c ff = 0 rms output noise vs feedfor ward capacitor (c ff ) 5v 10hz to 100khz output noise c ref/byp = 10nf, c ff = 0 5v 10hz to 100khz output noise c ref/byp = 10nf, c ff = 10nf output noise spectral density vs c ref/byp , c ff = 0 rms output noise vs c ref/byp , v out = 0.6v rms output noise vs load current c ref/byp = 10nf, c ff = 0 frequency (hz) 10 0.01 output noise spectral densit y ( v / hz ) 1 0.1 10 100 10k 100k 3063 g28 1k 0.6v 1.2v 2.5v 3.3v 5v c out = 10f i l = 200ma frequency (hz) 10 0.01 output noise spectral densit y ( v / hz ) 1 0.1 10 100 10k 100k 3063 g29 1k c out = 10f i l = 200ma v out = 5v c ref/byp = 100pf c ref/byp = 10nf c ref/byp = 1nf v out = 0.6v frequency (hz) 10 0.01 output noise spectral densit y ( v / hz ) 1 0.1 10 100 10k 100k 3063 g30 1k c ff = 100pf c ff = 1nf c ff = 0 c ff = 10nf v out = 5v c out = 10f i l = 100ma load current (ma) 0.01 0 output noise vol t age ( v rms ) 70 80 90 100 40 50 60 30 20 10 110 0.1 10 100 3063 g31 1 c ref/byp = 10nf c ref/byp = 100pf c ref/byp = 10pf c ref/byp = 0 c ref/byp = 1nf f = 10hz to 100khz c out = 10f load current (ma) 0.01 0 output noise vol t age ( v rms ) 70 80 90 100 110 120 130 140 150 40 50 60 30 20 10 160 0.1 10 100 3063 g32 1 f = 10hz to 100khz c out = 10f v out = 0.6v v out = 1.2v v out = 2.5v v out = 3.3v v out = 5v feedforward capacitor, c ff (nf) 0.01 0 output noise vol t age ( v rms ) 70 80 90 100 110 120 40 50 60 30 20 10 130 0.1 10 3063 g33 1 f = 10hz to 100khz c ref/byp = 10nf c out = 10f i fb-divider = 10a i load = 200ma v out = 5v v out = 0.6v v out = 3.3v v out = 1.2v v out = 2.5v 1ms/div 3063 g34 c out = 10f i load = 200ma v out 100v/div 1ms/div 3063 g35 c out = 10f i load = 200ma v out 100v/div t a = 25c, unless otherwise noted. lt 3063 3063f
9 for more information www.linear.com/LT3063 typical p er f or m ance c harac t eris t ics shdn transient response c ref/byp = 10nf start-up t ime vs ref/byp capacitor t ransient response, v out = 5v load dump, v in = 12v to 45v shdn t ransient response c ref/byp = 0 1ms/div 12v 45v 3063 g36 c out = 10f c ref/byp = c ff = 10nf i fb-divider = 10a v out 5mv/div v in 10v/div 2ms/div 3063 g37 c out = 10f c ff = 0 v out 2v/div r l = 500k ref/byp 500mv/div shdn 1v/div 2ms/div 3063 g38 c out = 10f c ff = 0 v out 2v/div r l = 500k ref/byp 500mv/div shdn 1v/div ref/byp capacitor (nf) 0.01 0.01 st ar t -up time (ms) 10 0.1 1 100 10 100 0.1 3063 g39 1 c ff = 0 t a = 25c, unless otherwise noted. lt 3063 3063f
10 for more information www.linear.com/LT3063 p in func t ions ref/byp ( pin 1): reference/ bypass. connecting a single capacitor from this pin to gnd bypasses the LT3063s reference noise and soft-starts the reference. a 10 nf by - pass capacitor typically reduces output voltage noise to 30v rms in a 10 hz to 100 khz bandwidth. soft-start time is directly proportional to the ref/byp capacitor value . if the LT3063 is placed in shutdown, ref/byp is actively pulled low by an internal device to reset soft-start. if low noise or soft-start per formance is not required, this pin must be left floating ( unconnected). do not drive this pin with any active cir cuitr y. adj ( pin 2): adjust. this pin is the error amplifiers invert - ing terminal . its typical bias current of 15 na flows out of the pin ( see cur ve of adj pin bias current vs t emperature in the t ypical per formance characteristics section). the adj pin voltage is 600mv referenced to gnd. out ( pins 3, 4): output. these pins supply power to the load. a minimum output capacitor of 3.3 f is required to prevent oscillations. large load transient applications require larger output capacitors to limit peak voltage transients. see the applications information section for more information on reverse output characteristics. the output voltage range is 600 mv to 19 v. if the LT3063 is placed in shutdown, out is actively discharged by an internal nmos device. gate drive is controlled to insure that a 10 f capacitor is discharged 90% in 2 ms or less. if in is driven low, out is actively discharged to ~800 mv. for out voltages greater than 6 v, current limit foldback is implemented to protect the nmos device and discharge rates increase. see the applications information section for more information. in ( pins 5, 6): input. these pins supply power to the device. the LT3063 requires a bypass capacitor at in if the device is located more than six inches from the main input filter capacitor. in general, the output impedance of a batter y rises with frequency, so it is advisable to include a bypass capacitor in batter y-powered cir cuits. a bypass capacitor in the range of 1 f to 10 f suffices. see input capacitance and stability in the application information section for more information. the LT3063 withstands reverse voltages on the in pin with respect to the gnd and out pins. in a reversed input situation, such as the batter y plugged in backwards, the LT3063 behaves as if a large value resistor is in series with its input. limited reverse current flows into the LT3063 and no reverse voltage appears at the load. the device protects itself and the load. shdn ( pin 7): shutdown. pulling the shdn pin low puts the LT3063 into a low power state and turns the output off. drive the shdn pin with either logic or an open collec - tor/drain with a pull-up resistor. the resistor supplies the pull-up current to the open collector/drain logic, normally several microamperes, and the shdn pin current, typi - cally less than 3 a. if unused, connect the shdn pin to v in . the LT3063 does not function if the shdn pin is not connected. the shdn pin cannot be driven below gnd unless tied to the in pin. if the shdn pin is driven below gnd while in is powered, the output will turn on. shdn pin logic cannot be referenced to a negative rail. gnd ( pin 8, exposed pad pin 9): ground. connect the bottom of the external resistor divider that sets the output voltage directly to gnd for optimum regulation. ti e the exposed pad pin 9 directly to pin 8 and the pcb ground. this exposed pad provides enhanced thermal per formance with its connection to the pcb ground. see the applica - tions information section for thermal considerations and calculating junction temperature. lt 3063 3063f
11 for more information www.linear.com/LT3063 the LT3063 is a 200ma low dropout regulator with shutdown. the device is capable of supplying 200 ma at a typical dropout voltage of 300 mv and operates over a 1.6v to 45v input range. a single external capacitor provides programmable low noise reference per formance and output soft-start func - tionality. for example, connecting a 10 nf capacitor from the ref/byp pin to gnd lowers output noise to 30 v rms over a 10 hz to 100 khz bandwidth. this capacitor also soft-starts the reference and prevents output voltage overshoot at turn-on. the LT3063s quiescent current is merely 45 a, while providing fast transient response with a 3.3 f minimum low esr ceramic output capacitor. in shutdown, quies - cent current is less than 3 a and the reference soft-start capacitor and output are reset. the LT3063 optimizes stability and transient response with low esr, ceramic output capacitors. the LT3063 does not require the addition of esr as is common with other regulators. the LT3063 has an adjustable output and typically provides 0.1% line regulation and 0.1% load regulation. a cur ve of load regulation appears in the t ypical per formance characteristics section. the LT3063 discharges the output in shutdown. internal protection cir cuitr y includes reverse- batter y protection , reverse-current protection, current limit with foldback and thermal shutdown. adjustable operation the LT3063 has an output voltage range of 0.6 v to 19 v. the output voltage is set by the ratio of two external resis - tors as shown in figure 1. the device ser vos the output to maintain the adj pin voltage at 0.6 v referenced to ground. the current in r1 is then equal to 0.6 v/r1 and the current in r2 is the current in r1 plus the adj pin bias current. the adj pin bias current , 15 na at 25o c, flows through r2 into the adj pin. calculate the output voltage using the formula in figure 1. the value of r1 should be no greater than 61.9 k to provide a minimum 10 a load current for stability. the divider does not add to quiescent current in a pplica t ions i n f or m a t ion figure 1. adjustable operation shutdown because the output is turned off and the divider current is zero. cur ves of adj pin v oltage vs t emperature and adj pin bias current vs t emperature appear in the t ypical per formance characteristics. 3063 f01 in shdn out adj gnd ref/byp l t3063 v in v out r2 r1 v o u t = 0.6 v 1 + r 2 r 1 ! " # $ % & ? i a d j ? r 2 ( ) v a d j = 0.6 v i a d j = 15 na a t 25 c o u tp u t r a n g e = 0.6 v t o 19 v the LT3063 is tested and specified with the adj pin tied to the out pin for an output voltage of 0.6 v. specifications for output voltages greater than 0.6 v are proportional to the ratio of the desired output voltage to 0.6 v: v out /0.6v. for example, load regulation for an output current change of 1 ma to 200 ma is C0.3mv typical at v out = 0.6 v. at v out = 12v, load regulation is: 12 v 0.6v ? ?0.3m v ( ) = ?6 m v t able 1 shows 1% resistor divider values for some common output voltages with a resistor divider current of 10a. t able 1. output v oltage resistor divider v alues v out r1 r2 1.2v 60.4k 60.4k 1.5v 59k 88.7k 1.8v 59k 118k 2.5v 60.4k 191k 3v 59k 237k 3.3v 61.9k 280k 5v 59k 432k lt 3063 3063f
12 for more information www.linear.com/LT3063 a pplica t ions i n f or m a t ion bypass capacitance, output v oltage noise and t ransient response the LT3063 regulator provides low output voltage noise over the 10 hz to 100 khz bandwidth while operating at full load with the addition of a bypass capacitor ( c ref/byp ) from the ref/byp pin to gnd. a good quality low leak - age capacitor is recommended. this capacitor bypasses the reference of the regulator, providing a low frequency noise pole for the internal reference. with the use of 10nf for c ref/byp , the output voltage noise decreases to as low as 30v rms when the output voltage is set for 0.6v . for higher output voltages ( generated by using a resistor divider), the output voltage noise gains up accordingly when using c ref/byp by itself. to lower the output voltage noise for higher output volt - ages, include a feedfor ward capacitor ( c ff ) from v out to the adj pin. a good quality, low leakage capacitor is recommended. this capacitor bypasses the error amplifier of the regulator, providing a low frequency noise pole. with the use of 10 nf for both c ff and c ref/byp , output voltage noise decreases to 30 v rms when the output voltage is set to 5 v by a 10 a feedback resistor divider . if the cur - rent in the feedback resistor divider is doubled, c ff must also be doubled to achieve equivalent noise per formance. higher values of output voltage noise may be measured if care is not exer cised with regard to cir cuit layout and testing. crosstalk from nearby traces can induce unwanted n o i s e o n to t h e l t 3 0 6 3 s o u tp u t . p o w e r s u p pl y r i p pl e r e j e c - tion must also be considered. the LT3063 regulator does not have unlimited power supply rejection and will pass a small portion of the input noise through to the output. using a feedfor ward capacitor ( c ff ) from v out to the adj pin has the added benefit of improving transient response for output voltages greater than 0.6 v. with no feedfor ward capacitor, the settling time will increase as the output voltage is raised above 0.6 v. use the equation in figure 2 to determine the minimum value of c ff to achieve a transient response that is similar to 0.6 v output voltage per formance regardless of the chosen output voltage ( see f ig ure 3 a nd t r an si en t r es pon se i n th e t y pi c al p er for ma nc e characteristics section). during start-up, the internal reference soft-starts if a refer - ence bypass capacitor is present. regulator startup time is directly proportional to the size of the bypass capacitor, slowing to 6 ms with a 10 nf bypass capacitor ( see shdn t ransient response vs ref/byp capacitor in the t ypical per formance characteristics section). the reference by - pass capacitor is actively pulled low during shutdown to reset the internal reference. start-up time is also affected by the use of a feedfor ward capacitor. start-up time is directly proportional to the size of the feedfor ward capacitor and output voltage, and is inversely proportional to the feedback resistor divider cur - rent, slowing to 15 ms with a 10 nf feedfor ward capacitor and a 10 f output capacitor for an output voltage set to 5v by a 10a feedback resistor divider. output capacitance the LT3063 regulator is stable with a wide range of output capacitors. the esr of the output capacitor affects stabil - ity, most notably with small capacitors. use a minimum output capacitor of 3.3 f with an esr of 3 or less to prevent oscillations. the LT3063 is a micropower device 3063 f02 in shdn out adj gnd ref/byp LT3063 v in v out c ref/byp c ff c out r2 r1 c f f 10 nf 10a ? i f b ? d i v i d e r ( ) i f b ? d i v i d e r = v o u t r1 + r2 100s/div v out = 5v c out = 10f i fb-divider = 10a 0 1nf 10nf load current 200ma/div feedforward capacitor, c ff 100pf 3063 f03 v out 100mv/div figure 2. feedforward capacitor for fast transient response figure 3. t ransient response vs feedfor ward capacitor lt 3063 3063f
13 for more information www.linear.com/LT3063 and output load transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient re - sponse for larger load current changes. bypass capacitors , used to decouple individual components powered by the LT3063, will increase the effective output capacitor value . for applications with large load current transients, a low esr ceramic capacitor in parallel with a bulk tantalum capacitor often provides an optimally damped response. give extra consideration to the use of ceramic capacitors. manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across tempera - ture and applied voltage. the most common dielectrics are specified with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics provide high c-v products in a small package at low cost, but exhibit strong voltage and temperature coefficients as shown in figures 4 and 5. when used with a 5 v regulator, a 16 v 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2 f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics yield much more stable characteristics and are more suitable for use as the output capacitor. the x7r type works over a wider temperature range and has better temperature stability, while the x 5 r is less expensive and is available in higher values. care still must be exer cised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be significant enough to drop capacitor values below appropriate levels. capaci - tor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. v oltage and temperature coefficients are not the only sour ces of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or micro - phone works . for a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise. a ceramic capacitor produced the trace a pplica t ions i n f or m a t ion in figure 6 in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. dc bias voltage (v) change in value (%) 3063 f04 20 0 ?20 ?40 ?60 ?80 ?100 0 4 8 10 2 6 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) ?50 40 20 0 ?20 ?40 ?60 ?80 ?100 25 75 3063 f05 ?25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f figure 4. ceramic capacitor dc bias characteristics figure 5. ceramic capacitor t emperature characteristics figure 6. noise resulting from t apping on a ceramic capacitor 4ms/div 3063 f06 v out 500 v /div v out = 0.6v c out = 10f c ref/byp = 10nf i load = 100ma lt 3063 3063f
14 for more information www.linear.com/LT3063 a pplica t ions i n f or m a t ion input capacitance and stability low esr, ceramic input bypass capacitors are acceptable for applications without long input leads. however, appli - cations connecting a power supply to an LT3063 cir cuits in and gnd pins with long input wires combined with a low esr, ceramic input capacitor are prone to voltage spikes, reliability concerns and application-speci?c board oscillations. the input wire inductance found in many batter y-powered applications, combined with the low esr ceramic input capacitor, forms a high q lc resonant tank cir cuit. in some instances this resonant frequency beats against the output current dependent ldo bandwidth and inter feres with proper operation. simple cir cuit modifications/solu - tions are then required. this behavior is not indicative of LT3063 instability, but is a common ceramic input bypass capacitor application issue. the self-inductance, or isolated inductance, of a wire is directly proportional to its length. wire diameter is not a major factor on its self-inductance. for example, the self- inductance of a 2- aw g isolated wire ( diameter = 0.26") is about half the self-inductance of a 30- aw g wire ( diameter = 0.01"). one foot of 30- aw g wire has approximately 465nh of self-inductance. tw o methods can reduce wire self - inductance. one method divides the current ? owing towards the LT3063 between two parallel conductors. in this case, the farther apart the wires are from each other, the more the self-inductance is reduced; up to a 50% reduction when placed a few inches apart. splitting the wires connects two equal inductors in parallel, but placing them in close proximity creates mutual inductance adding to the self-inductance. the second and most effective way to reduce overall inductance is to place both for ward and return current conductors ( the input and gnd wires) in ver y close proximity. tw o 30- aw g wires separated by only 0.02, used as for ward and return current conductors, reduce the overall self-inductance to approximately one-?fth that of a single isolated wire. if a ba tt er y, mo unt ed i n c los e pr ox im ity , po we rs th e lt 30 63 , a 1 f input capacitor suffices for stability. however, if a distant supply powers the LT3063, use a larger value input capacitor. use a rough guideline of 1 f ( in addition to the 1f minimum) per 8 inches of wire length. the minimum input capacitance needed to stabilize the application also varies with power supply output impedance variations. placing additional capacitance on the LT3063s output also helps. however, this requires an order of magnitude more capacitance in comparison with additional LT3063 input bypassing. series resistance between the supply and the LT3063 input also helps stabilize the applica - tion; as little as 0.1 to 0.5 suffices. this impedance dampens the lc tank cir cuit at the expense of dropout voltage. a better alternative is to use higher esr tantalum or electrolytic capacitors at the LT3063 input in place of ceramic capacitors. overload recovery like many ic power regulators, the LT3063 has safe oper - ating area protection. the safe area protection decreases current limit as input - to - output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. the protective design provides some output current at all values of input-to- output voltage up to the device breakdown. when power is first applied, as input voltage rises, the output follows the input, allowing the regulator to start up into ver y heavy loads. during start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. with a high input voltage, a problem can occur wherein removal of an output short will not allow the output to recover. the problem occurs with a heavy output load when the input voltage is high and the output voltage is low. com - mon situations include immediately after the removal of a short-cir cuit or if the shutdown pin is pulled high after the input voltage has already been turned on. the load line for such a load may intersect the output current cur ve at two points. if this happens, there are two stable output operat - ing points for the regulator. with this double intersection, the input power supply may need to be cycled down to zero and brought up again to make the output recover. lt 3063 3063f
15 for more information www.linear.com/LT3063 thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125 c for l t 3 0 6 3 e , l t 3 0 6 3 i o r 1 5 0 c f o r l t 3 0 6 3 m p , l t 3 0 6 3 h ) . t w o components comprise the power dissipated by the device: 1. output current multiplied by the input/output voltage differential: i out ? ( v in C v out ), and 2. gnd pin current multiplied by the input voltage : i gnd ? v in gnd pin current is determined using the gnd pin current cur ves in the t ypical per formance characteristics section. power dissipation equals the sum of the two components listed above. the LT3063 regulator has internal thermal limiting that pro - tects the device during overload conditions. for continuous normal conditions, the maximum junction temperature of 125c ( e-grade, i-grade) or 150 c ( mp-grade, h-grade) must not be exceeded. carefully consider all sour ces of thermal resistance from junction to ambient including other heat sour ces mounted in proximity to the LT3063. the undersides of the LT3063 packages have exposed metal from the lead frame to the die attachment. the package allows heat to directly transfer from the die junction to the printed cir cuit board metal to control maximum operating junction temperature. the dual-in- line pin arrangement allows metal to extend beyond the ends of the package on the topside ( component side) of a pcb. connect this metal to gnd on the pcb. the multiple in and out pins of the LT3063 also assist in spreading heat to the pcb. for sur face mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener - ated by power devices. a pplica t ions i n f or m a t ion the following tables list thermal resistance for several different board sizes and copper areas. all measurements were taken in still air on a 4 layer fr-4 board with 1 oz solid internal planes and 2 oz top/bottom external trace planes with a total board thickness of 1.6 mm. the four layers were electrically isolated with no thermal vias present. pcb layers, copper weight, board layout and thermal vias will affect the resultant thermal resistance. for more information on thermal resistance and high thermal conductivity test boards, refer to jedec standard jesd51, notably jesd51-12 and jesd51-7. achieving low thermal resistance necessitates attention to detail and careful pcb layout. t able 2. measured thermal resistance for dfn package copper area board area (mm 2 ) thermal resist ance (junction-to-ambient) topside* (mm 2 ) backside (mm 2 ) 2500 2500 2500 38c/w 1000 2500 2500 38c/w 225 2500 2500 40c/w 100 2500 2500 45c/w *device is mounted on topside t able 3. measured thermal resistance for msop package copper area board area (mm 2 ) thermal resist ance (junction-to-ambient) topside* (mm 2 ) backside (mm 2 ) 2500 2500 2500 29c/w 1000 2500 2500 30c/w 225 2500 2500 32c/w 100 2500 2500 45c/w *device is mounted on topside lt 3063 3063f
16 for more information www.linear.com/LT3063 a pplica t ions i n f or m a t ion calculating junction t emperature example: given an output voltage of 2.5 v, an input volt - age range of 12 v 5%, an output current range of 0 ma to 50 ma and a maximum ambient temperature of 85 c, what will the maximum junction temperature be? the power dissipated by the device equals: i out(max) ? ( v in(max) Cv out ) + i gnd ? v in(max) where, i out(max) = 50ma v in(max) = 12.6v i gnd at (i out = 50ma, v in = 12v) = 1ma so, p = 50ma ? (12.6 v C 2.5v) + 1ma ? 12.6 v = 0.518w using a dfn package, the thermal resistance will be in the range of 38 c/w to 45 c/w depending on the copper area. so the junction temperature rise above ambient is approximately equal to: 0.518 w ? 45 c/w = 23.3c the maximum junction temperature equals the maximum ambient temperature plus the maximum junction tempera - ture rise above ambient or: t jmax = 85c + 23.3c = 108.3c output discharge the LT3063 includes a low resistance nmos device which rapidly discharges the output voltage if the part is put in shutdown mode. for a 2.9 v output with a 10 f decoupling capacitor, the nmos discharges the output to 290 mv in 750s if shdn is driven low. control cir cuitr y drives the gate of the nmos high if either the shdn pin or the in pin are driven low . in the case where the in pin is driven to ground, the nmos rapidly discharges the out pin to the threshold voltage of the nmos, approximately 800 mv. from 800 mv, the external load discharges the out pin at a reduced rate. the control cir cuitr y implements protection features which allow the out pin to be driven from C1 v to 20 v without damaging the LT3063 . current limit foldback for output voltages greater than 6v protects the nmos pull-down, but increases discharge times for higher output voltages . figure 7. discharge t ime vs output v oltage output vol t age (v) 0 0 output discharge time (ms) 3.5 1.0 1.5 2.0 2.5 3.0 0.5 4.0 2 10 12 14 16 18 20 4 6 3063 f07 8 c out = 10f v in = v out + 1v output discharge foldback st ar ts protection features the LT3063 incorporates several protection features that make it ideal for use in batter y-powered cir cuits. in ad - dition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device also protects against reverse-input voltages and reverse output-to-input voltages. current limit protection and thermal overload protection protect the device against current overload conditions at the output of the device. the typical thermal shutdown temperature is 165 c . for normal operation, do not exceed a junction temperature of 125 c ( LT3063e, LT3063i) or 150c (LT3063mp, LT3063h). lt 3063 3063f
17 for more information www.linear.com/LT3063 the LT3063 in pin withstands reverse voltages of 50 v . the device limits current flow to less than 1 ma ( typically less than 250 a) and no negative voltage appears at out. the device protects both itself and the load against batteries that are plugged in backwards. the shdn pin cannot be driven below gnd unless tied to the in pin. if the shdn pin is driven below gnd while in is powered, the output will turn on. shdn pin logic cannot be referenced to a negative rail. the LT3063 incurs no damage if the adj pin is pulled above or below ground by 50 v. if the input is left open cir cuit or grounded, the adj pin per forms like a large resistor (typically 30 k) in series with a diode when pulled above or below ground. several different input/output conditions can occur, some temporarily until the output capacitor is discharged by the LT3063. the output voltage may be held up temporarily or other wise while the input is pulled to ground, pulled to some intermediate voltage or left open-cir cuit. current a pplica t ions i n f or m a t ion flow back into the out pin follows the cur ve shown in figure 8. if the LT3063's in pin is for ced below the out pin or the out pin is pulled above the in pin, regardless of the state of the shdn pin, input current typically drops to less than 3 a. if in is pulled near 0 v, the output discharge pull-down nmos turns on, regardless of the state of the shdn pin. the gate drive for the pull-down is supplied by the output voltage. figure 8. lt3603 reverse output current v out (v) 0 0 reverse current (a) 45 40 30 35 20 25 5 10 15 50 2 12 14 16 18 20 4 6 8 3063 f08 10 v in = v shdn = 2.1v v adj = v out i out lt 3063 3063f
18 for more information www.linear.com/LT3063 p ackage descrip t ion please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 ref 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb8) dfn 0106 rev a 0.23 0.05 0.45 bsc pin 1 notch r = 0.20 or 0.25 45 chamfer 0.25 0.05 1.35 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.10 0.05 0.70 0.05 3.50 0.05 package outline 0.45 bsc 1.35 0.10 1.35 0.05 1.65 0.10 1.65 0.05 dcb package 8-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1718 rev a) lt 3063 3063f
19 for more information www.linear.com/LT3063 information furnished by linear t echnology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear t echnology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8e) 0213 rev k 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. dra wing not to scale 3. dimension does not include mold flash, protrusions or ga te burrs. mold flash, protrusions or ga te burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarit y (bot tom of leads af ter forming) shall be 0.102mm (.004") max 6. exposed p ad dimension does include mold flash. mold flash on e-p ad shall not exceed 0.254mm (.010") per side. 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 ty p detail ?a? det ail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 8 1 bot tom view of exposed p ad op tion 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 1.68 (.066) 1.88 (.074) 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.889 0.127 (.035 .005) recommended solder pad layout 0.65 (.0256) bsc 0.42 0.038 (.0165 .0015) typ 0.1016 0.0508 (.004 .002) det ail ?b? det ail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref ms8e package 8-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1662 rev k) lt 3063 3063f
20 for more information www.linear.com/LT3063 ? linear technology corporation 2014 l t 0614 ? printed in usa linear t echnology corporation 1 6 3 0 m c c a r t h y b l v d . , m i l p i t a s , c a 9 5 0 3 5 - 7 4 17 ( 4 0 8 ) 4 3 2 - 1 9 0 0 f a x : ( 4 0 8 ) 4 3 4 - 0 5 0 7 w w w . l i n e a r . c o m / l t 3 0 6 3 typical a pplica t ion r ela t e d p ar t s pa r t number descrip tion comments lt1761 100ma, low noise ldo 300mv dropout v oltage, low noise: 20v rms , v in = 1.8v to 20v , thinsot? package lt1762 150ma, low noise ldo 300mv dropout v oltage, low noise: 20v rms , v in = 1.8v to 20v , ms8 package lt1763 500ma, low noise ldo 300mv dropout v oltage, low noise: 20v rms , v in = 1.8v to 20v , so8, 3mm 4mm dfn-12 package lt1962 300ma, low noise ldo 270mv dropout v oltage, low noise: 20v rms , v in = 1.8v to 20v , ms8 package lt1964 200ma, low noise, negative ldo 340mv dropout v oltage, low noise 30v rms , v in = C1.8v to C20v , thinsot, 3mm 3mm dfn-8 packages lt3008 20ma, 45v , 3a i q micropower ldo 300mv dropout v oltage, low i q : 3a, v in = 2v to 45v , v out = 0.6v to 44.5v ; thinsot and 2mm 2mm dfn-6 packages lt3009 20ma, 3a i q micropower ldo 280mv dropout v oltage, low i q : 3a, v in = 1.6v to 20v , 2mm 2mm dfn-6 and sc70 packages lt3050 100ma, low noise linear regulator with precision current limit and diagnostic functions. 340mv dropout v oltage, low noise: 30v rms , v in : 1.6v to 45v , v out : 0.6v to 44.5v , programmable precision current limit: 5%, programmable minimum i out monitor , output current monitor , fault indicator , reverse protection; 12-lead 3mm 2mm dfn and msop packages. lt3060 45v v in , micropower, low noise, 100ma low dropout linear regulator input v oltage range: 1.6v to 45v, quiescent current: 40a, dropout v oltage: 300mv, low noise: 30v rms (10hz to 100khz), adjustable output: v ref = 600mv, 8-lead 2mm x 2mm dfn and 8-lead thinsot lt3082 200ma, parallelable, single resistor, low dropout linear regulator outputs may be paralleled for higher output, current or heat spreading, wide input v oltage range: 1.2v to 40v low v alue input/output capacitors required: 0.22f, single resistor sets output v oltage, initial set pin current accuracy: 1%, low output noise: 40v rms (10hz to 100khz) reverse-batter y protection, reverse-current protection; 8-lead sot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages lt3085 500ma, parallelable, low noise, low dropout linear regulator 275 mv dropout v oltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set, directly parallelable (no op amp required), stable with ceramic capacitors; ms8e and 2mm 3mm dfn-6 packages lt3092 200ma 2-t erminal programmable current sour ce programmable 2-t erminal current sour ce, maximum output current: 200ma, wide input v oltage range: 1.2v to 40v, resistor ratio sets output current, initial set pin current accuracy: 1%, current limit and thermal shutdown protection, reverse-v oltage protection, reverse-current protection; 8-lead sot-23, 3-lead sot-223 and 8-lead 3mm 3mm dfn packages 3063 t a02 in shdn out adj gnd byp l t3063 v in 2.3v v out 1.8v 200ma 1 f 10f 118k 1% 59k 1% 0.01 f 1.8v low noise regulator lt 3063 3063f

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